The present invention relates to a high voltage generating circuit for a semiconductor memory device.
A conventional memory cell of a dynamic random access memory (DRAM) device includes an NMOS transistor and a capacitor. The NMOS transistor is between the capacitor and a bit line and has a gate coupled to a word line. When a voltage on the word line is high, the NMOS transistor turns on to transmit data stored in the memory cell to the bit line or to store data from the bit line in the memory cell. When transferring a data signal having a logic high level, the NMOS transistor can cause a voltage drop because the gate-to-source voltage difference of the NMOS transistor must be greater than or equal to the threshold voltage of the NMOS transistor. Accordingly, DRAMs commonly use a high voltage generating circuit that generates a high voltage signal at a level higher that the logic high level of the data signals. When the word line is at the high voltage from the high voltage generating circuit, the NMOS transistor can transfer a logic high data signal without the voltage drop associated with the transistor""s threshold voltage.
DRAMs also commonly include an NMOS transistor as a bit line select transistor to control the transmission of data between a data line and a bit line. A data signal at the logic high level can be transmitted without a voltage drop if the high voltage signal from the high voltage generating circuit is applied to a gate of the NMOS select transistor.
A high voltage generating circuit of a conventional semiconductor memory device includes a primary high voltage detector, a primary high voltage generator, a secondary high voltage detector, and a secondary high voltage generator. The primary high voltage detector and generator generate and monitor a high voltage signal in a standby mode and in an active mode. The secondary high voltage detector and generator supplement operation of the primary high voltage detector and generator in the active mode. More specifically, the charge loss or current from the high voltage is typically greater than the primary high voltage generator can supply without a drop in the output voltage. Accordingly, the secondary high voltage generator operates to maintain the high voltage level. However, a fast semiconductor memory device requires that a word line be enabled within a very short time after an active command. The conventional primary and secondary high voltage detectors cannot easily detect a voltage drop and direct the primary and secondary high voltage generators to compensate for the voltage drop quickly enough to charge word lines to the high voltage level when the word line is enabled.
In accordance with an aspect of the present invention, a high voltage generating circuit of a semiconductor memory device maintains a high voltage after an active command and before a word line is enabled. To accomplish this, one embodiment of the present invention is a high voltage generating circuit includes a secondary high voltage generator and a primary high voltage generator. The secondary high voltage generator responds to an active signal designating an active mode, generates a second signal upon detecting a drop in a high voltage signal and/or in response to a first signal, and boosts the high voltage signal in response to the second signal. The primary high voltage generator generates the first signal in response to detecting a drop in the high voltage level in standby mode and in active mode, and boosts the high voltage level in response to the first signal.
According to another embodiment of the present invention, a high voltage generating circuit of a semiconductor memory device includes a secondary high voltage detector, a secondary high voltage generator, a primary high voltage detector, and a primary high voltage generator. The secondary high voltage detector responds to an active or enable signal and generates a second signal when a drop in a high voltage signal is detected and/or in response to a first signal. The primary high voltage detector generates the first signal upon detecting the drop of the high voltage signal in active and standby modes. The primary high voltage generator boosts the high voltage signal in response to the first signal. Accordingly, the secondary generator can respond more quickly and boost the high voltage signal when entering the active mode while the primary detector signals a voltage drop.